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Analysis of Cache Memories in Highly Parallel Systems (Classic Reprint)
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Excerpt from Analysis of Cache Memories in Highly Parallel Systems Analogous to reducing the effective memory access time in uniprocessor sys tems, a memory hierarchy can be used in parallel processor systems that employ a PE to central memory connection network the hierarchy comprising a local memory associated with each PE and a large central memory. The inclusion of a local memory reduces the effective memory access time since the resulting access time is an average of the network and local memory latencies. Moreover, since the local memory services a percentage of all memory requests. Network traffic is diminished, thus reducing network latency. The indiscriminate use of a local memory, however, can introduce memory coherence violations a memory system. About the Publisher Forgotten Books publishes hundreds of thousands of rare and classic books. Find more at www.forgottenbooks.com This book is a reproduction of an important historical work. Forgotten Books uses state-of-the-art technology to digitally reconstruct the work, preserving the original format whilst repairing imperfections present in the aged copy. In rare cases, an imperfection in the original, such as a blemish or missing page, may be replicated in our edition. We do, however, repair the vast majority of imperfections successfully; any imperfections that remain are intentionally left to preserve the state of such historical works.
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